CMOS FETs are useful as semiconductor switches operating at a relatively high voltage with low power consumption. According to conventional techniques, they are produced in a silicon substrate of one conductivity type (e.g. n) a region of which is subjected to implantation of impurities of the opposite conductivity type (p) to form a so-called well serving as the site of one of the two complementary FETs, specifically of the n-channel FET in the case of a p-well. An adjoining region of the original conductivity type then becomes the site of the other FET.
It is, of course, desirable that the two MOSFETs be spaced as closely as possible from one another and from other components of the same silicon wafer. In order to avoid undesirable interaction between such closely spaced components, it is known to separate them from one another by barriers which may be in the shape of surrounding guard rings or strips and which in the case of field-effect transistors are referred to as channel stops. These channel stops are generally of the same conductivity type as the adjoining substrate region carrying the protected MOSFET, but with a higher impurity concentration.
Commonly owned U.S. Pat. No. 4,277,291, applied for by me jointly with Giuseppe Ferla, discloses a process for the production of CMOS FETs with contiguous channel stops which, in contradistinction to earlier techniques, requires the formation of only one heavy oxide layer. According to the patented process, a first and a second patch of shielding material such as silicon nitride are formed on an oxide layer overlying a silicon substrate of one conductivity type, above spaced-apart first and second regions of that substrate, whereupon impurities of that one conductivity type are injected through the oxide layer into zones of the substrate immediately adjoining both regions, these zones including an intermediate section which separates the two regions from each other. Next, the first patch and an immediately adjoining first zone of the oxide layer--including a portion thereof overlying part of the intermediate section--are covered with a masking layer while the second patch and an immediately adjoining second zone of the oxide layer--including a portion thereof overlying another part of the intermediate section--are left uncovered. Impurities of the opposite conductivity type are then injected into the substrate through the second patch and through the second zone of the oxide layer in a quantity sufficient to overcompensate the effect of the impurities of the first-mentioned conductivity type which were previously injected through that second zone and to implant the impurities of the opposite conductivity type with a relatively high concentration in a substrate portion underlying that second zone and with a lower concentration in the second region bounded thereby. Following removal of the masking layer, the substrate is subjected to a heat treatment whereby the oxide layer already present thereon is caused to grow, especially in the areas free from the patches. Thereafter the two patches are removed together with underlying portions of the oxide layer so as to expose both the first and the second region of the substrate except for a residue of the oxide layer which extends across each of these regions to serve as an insulating gate support while dividing each region into source and drain areas. Finally, impurities of the first-mentioned conductivity type are introduced into the source and drain areas of the second region while impurities of the opposite conductivity type are introduced into corresponding areas of the first region.
As is known, the conduction threshold of a MOSFET is a function of the width of its channel relative to that of the overall transistor area. The process of the prior patent, while otherwise very useful, has the drawback of considerably restricting the relative width of that channel whose conductivity type is the same as that of the substrate (n in the embodiment specifically described in the patent). This is disadvantageous when a given wafer is to be provided with a maximum number of CMOS FETs each occupying only a small fraction of the available surface area. When such a wafer becomes part of an integrated circuit whose constituents vary widely in channel width and therefore in conduction threshold, the layout of that circuit is rather complex.